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| September 2005 rev 1.3 3.3V `SpreadTrak' Zero Delay Buffer Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer "ASM5P23S04A Configurations Table". Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of two outputs each. Less than 200pS Cycle-to-cycle jitter (-1, -1H, -2, -2H). Available in space saving, 8 pin 150-mil SOIC package. 3.3V operation. Advanced 0.35 CMOS technology. Industrial temperature available. `SpreadTrak'. The ASM5P23S04A (Refer is ASM5P23S04A the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS. The ASM5P23S04A has two banks of two outputs each. Multiple ASM5P23S04A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500pS. available in two different configurations "ASM5P23S04A Configurations Table). The ASM5P23S04A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P23S04A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. Functional Description ASM5P23S04A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in a 8 pin package. The part has an on-chip PLL, which locks to an input clock, presented on The ASM5P23S04A-2 allows the user to obtain REF and 1/2X or 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Alliance Semiconductor 2575 Augustine Drive * Santa Clara, CA * Tel: 408.855.4900 * Fax: 408.855.4999 * www.alsc.com Notice: The information in this document is subject to change without notice. September 2005 rev 1.3 ASM5P23S04A Configurations ASM5P23S04A Device ASM5P23S04A-1 ASM5P23S04A-1H ASM5P23S04A-2 ASM5P23S04A-2 ASM5P23S04A-2H ASM5P23S04A-2H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A Frequency Reference Reference Reference 2 X Reference Reference 2 X Reference Bank B Frequency Reference Reference Reference /2 Reference Reference/2 Reference `SpreadTrak' Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. ASM5P23S04A is designed so as not to filter off the Spread Spectrum feature of the Reference Input, 1500 assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization. 1000 REF-Input to CLKA/CLKB Delay (ps) 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 15 September 2005 rev 1.3 Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. To close the feedback loop of ASM5P23S04A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input ASM5P23S04A output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. Pin Configuration REF 1 CLKA1 2 CLKA2 3 GND 4 ASM5P23S04A 8 FBK 7 VDD 6 CLKB2 5 CLKB1 Pin Description for ASM5P23S04A Pin # 1 2 3 4 5 6 7 8 Pin Name REF1 CLKA12 CLKA22 GND CLKB12 CLKB2 2 VDD FBK Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A Ground Buffered clock output, bank B Buffered clock output, bank B 3.3V supply PLL feedback input Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 15 September 2005 rev 1.3 Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) ASM5P23S04A Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 Unit V V V C C C >2000 V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P23S04A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Description Min 3.0 0 Max 3.6 70 30 15 7 Unit V C pF pF pF Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz Load Capacitance, from 100MHz to 133MHz Input Capacitance3 Note: 3. Applies to both Ref Clock and FBK. 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 15 September 2005 rev 1.3 Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices ASM5P23S04A Parameter VIL VIH IIL IIH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current VIN = 0V Test Conditions Min Max 0.8 Unit V V 2.0 50.0 100.0 A A VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND VOL Output LOW Voltage 4 0.4 V VOH Output HIGH Voltage 4 2.4 V 45.0 IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) 32.0 mA 18.0 Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 15 September 2005 rev 1.3 Switching Characteristics for ASM5P23S04A Commercial Temperature Devices Parameter 1/t1 1/t1 1/t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -2H) Duty Cycle 5 = (t2 / t1) * 100 (-1, -2,-1H, -2H) t3 Output Rise Time 5 (-1, -2) Output Rise Time 5 (-1, -2) Output Rise Time 5 (-1H, -2H) Output Fall Time 5 (-1, -2) Output Fall Time 5 (-1, -2) Output Fall Time 5 (-1H, -2H) Output-to-output skew on same bank (-1, -2) 5 t5 Output-to-output skew (-1H, -2H) Output bank A -to- output bank B skew (-1, -2H) Output bank A to output bank B skew (-2) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge 5 Device-to-Device Skew 5 Output Slew Rate5 5 ASM5P23S04A Test Conditions 30pF load, All devices 15pF load, -1H, -2H devices 15pF load, -1, -2 devices Measured at 1.4V, FOUT = 66.66MHz 30pF load Measured at 1.4V, FOUT = <50MHz 15 pF load Measured between 0.8V and 2.0V 30pF load Measured between 0.8V and 2.0V 15pF load Measured between 0.8V and 2.0V 30pF load Measured between 2.0V and 0.8V 30pF load Measured between 2.0V and 0.8V 15pF load Measured between 2.0V and 0.8V 30pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67MHz, loaded outputs, 15pF load Min 15 15 15 40.0 Typ Max 100 133 133 Unit MHz MHz MHz % 50.0 60.0 45.0 50.0 55.0 % 2.20 nS t3 1.50 nS t3 1.50 nS t4 2.20 nS t4 1.50 nS t4 1.25 200 200 200 400 0 0 1 175 200 250 500 nS pS pS pS V/nS tJ Cycle-to-cycle jitter 5 (-1, -1H, -2H) Measured at 66.67MHz, loaded outputs, 30pF load Measured at 133MHz, loaded outputs, 15pF load pS 100 400 pS 375 tJ Cycle-to-cycle jitter 5 (-2) Measured at 66.67MHz, loaded outputs, 30pF load Measured at 66.67MHz, loaded outputs, 15pF load Stable power supply, valid clock presented on REF and FBK pins tLOCK PLL Lock Time 5 1.0 mS Note: 5. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 15 September 2005 rev 1.3 Operating Conditions for ASM5I23S04A Industrial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz Load Capacitance, from 100MHz to 133MHz Input Capacitance 6 ASM5P23S04A Description Min 3.0 -40 Max 3.6 85 30 15 7 Unit V C pF pF pF Note: 6. Applies to both Ref Clock and FBK. Electrical Characteristics for ASM5I23S04A Industrial Temperature Devices Parameter VIL VIH IIL IIH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current VIN = 0V VIN = VDD Test Conditions Min Max 0.8 Unit V V 2.0 50.0 100.0 A A VOL Output LOW Voltage 7 IOL = 8mA (-1, -2) IOH = 12mA (-1H, -2H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -2H) 0.4 V VOH Output HIGH Voltage 7 2.4 V Unloaded outputs 100MHz REF, Select inputs at VDD or GND IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 45.0 mA 35.0 20.0 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 15 September 2005 rev 1.3 Switching Characteristics for ASM5I23S04A Industrial Temperature Devices Parameter t1 t1 t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle 8 = (t2 / t1) * 100 (-1, -2, -1H, -2H) Duty Cycle 8= (t2 / t1) * 100 (-1, -2, -1H, -2H) t3 Output Rise Time 8 (-1, -2) Output Rise Time 8 (-1, -2) Output Rise Time 8 (-1H, -2H) Output Fall Time 8 (-1, -2) Output Fall Time 8 (-1, -2) Output Fall Time 8 (-1H, -2H) Output-to-output skew on same bank (-1, -2) 8 t5 Output-to-output skew (-1H, -2H) Output bank A -to- output bank B skew (-1, -2H) Output bank A -to- output bank B skew (-2) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge 8 Device-to-Device Skew 8 Output Slew Rate8 Test Conditions 30pF load, All devices 15pF load, -1H, -2H devices 15pF load, -1 and -2 devices Measured at 1.4V, FOUT = <66.66MHz 30pF load Measured at 1.4V, FOUT = <50MHz 15pF load Measured between 0.8V and 2.0V 30pF load Measured between 0.8V and 2.0V 15pF load Measured between 0.8V and 2.0V 30pF load Measured between 2.0V and 0.8V 30pF load Measured between 2.0V and 0.8V 15pF load Measured between 2.0V and 0.8V 30pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67MHz, loaded outputs, 15pF load tJ Cycle-to-cycle jitter 8 (-1, -1H, -2H) Measured at 66.67MHz, loaded outputs, 30pF load Measured at 133MHz, loaded outputs, 15pF load Cycle-to-cycle jitter 8 (-2) Measured at 66.67MHz, loaded outputs, 30pF load Measured at 66.67 MHz, loaded outputs, 15pF load Stable power supply, valid clock presented on REF and FBK pins ASM5P23S04A Min 15 15 15 40.0 Typ Max 100 133 133 Unit MHz MHz MHz % 50.0 60.0 45.0 50.0 55.0 % 2.50 nS t3 1.50 nS t3 1.50 nS t4 2.50 nS t4 1.50 nS t4 1.25 200 200 200 400 0 0 1 250 500 nS pS pS pS V/nS 180 pS 200 100 400 pS 380 tJ tLOCK PLL Lock Time 8 1.0 mS Note: 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 15 September 2005 rev 1.3 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V ASM5P23S04A All Outputs Rise/Fall Time OUTPUT 2.0 V 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V Output - Output Skew 1.4 V OUTPUT1 1.4 V OUTPUT2 t 5 Input - Output Propagation Delay VDD /2 INPUT VDD /2 OUTPUT t6 Device - Device Skew VDD /2 CLKOUT, Device 1 VDD /2 CLKOUT, Device 2 t 7 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 15 September 2005 rev 1.3 Test Circuits ASM5P23S04A TEST CIRCUIT # 1 VDD 0.1uF VDD 0.1uF GND GND CLKOUT OUTPUT CLOAD 0.1uF 0.1uF TEST CIRCUIT # 2 VDD OUTPUT VDD GND GND 1K 10pF 1K For parameter t8 (output skew rate) 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 15 September 2005 rev 1.3 Package Information 8-lead (150-mil) SOIC Package ASM5P23S04A E H D A2 A e B A 1 C L D Dimensions Symbol Min A1 A A2 B C D E e H L Inches Max 0.010 0.069 0.059 0.020 0.010 0.004 0.053 0.049 0.012 0.007 Millimeters Min Max 0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0 1.27 8 0.25 1.75 1.50 0.51 0.25 0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 15 September 2005 rev 1.3 Ordering Codes ASM5P23S04A Ordering Code Marking Package Type Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial ASM5P23S04A-1-08-SR ASM5P23S04A-1-08-ST ASM5I23S04A-1-08-SR ASM5I23S04A-1-08-ST ASM5P23S04A-1H-08-SR ASM5P23S04A-1H-08-ST ASM5I23S04A-1H-08-SR ASM5I23S04A-1H-08-ST ASM5P23S04A-2-08-SR ASM5P23S04A-2-08-ST ASM5I23S04A-2-08-SR ASM5I23S04A-2-08-ST ASM5P23S04A-2H-08-SR ASM5P23S04A-2H-08-ST ASM5I23S04A-2H-08-SR ASM5I23S04A-2H-08-ST ASM5P23S04AF-1-08-SR ASM5P23S04AF-1-08-ST ASM5I23S04AF-1-08-SR ASM5I23S04AF-1-08-ST 5P23S04A-1 5P23S04A-1 5I23S04A-1 5I23S04A-1 5P23S04A-1H 5P23S04A-1H 5I23S04A-1H 5I23S04A-1H 5P23S04A-2 5P23S04A-2 5I23S04A-2 5I23S04A-2 5P23S04A-2H 5P23S04A-2H 5I23S04A-2H 5I23S04A-2H 5P23S04AF-1 5P23S04AF-1 5I23S04AF-1 5I23S04AF-1 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 15 September 2005 rev 1.3 Ordering Codes (cont'd) ASM5P23S04A Ordering Code Marking Package Type Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial ASM5P23S04AF-1H-08-SR ASM5P23S04AF-1H-08-ST ASM5I23S04AF-1H-08-SR ASM5I23S04AF-1H-08-ST ASM5P23S04AF-2-08-SR ASM5P23S04AF-2-08-ST ASM5I23S04AF-2-08-SR ASM5I23S04AF-2-08-ST ASM5P23S04AF-2H-08-SR ASM5P23S04AF-2H-08-ST ASM5I23S04AF-2H-08-SR ASM5I23S04AF-2H-08-ST ASM5P23S04AG-1-08-SR ASM5P23S04AG-1-08-ST ASM5I23S04AG-1-08-SR ASM5I23S04AG-1-08-ST ASM5P23S04AG-1H-08-SR ASM5P23S04AG-1H-08-ST ASM5I23S04AG-1H-08-SR ASM5I23S04AG-1H-08-ST 5P23S04AF-1H 5P23S04AF-1H 5I23S04AF-1H 5I23S04AF-1H 5P23S04AF-2 5P23S04AF-2 5I23S04AF-2 5I23S04AF-2 5P23S04AF-2H 5P23S04AF-2H 5I23S04AF2H 5I23S04AFH 5P23S04AG-1 5P23S04AG-1 5I23S04AG-1 5I23S04AG-1 5P23S04AG-1H 5P23S04AG-1H 5I23S04AG-1H 5I23S04AG-1H 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Pb free 8-pin 150-mil SOIC-TUBE, Pb free 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 15 September 2005 rev 1.3 Ordering Codes (cont'd) ASM5P23S04A Ordering Code Marking Package Type Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial ASM5P23S04AG-2-08-SR ASM5P23S04AG-2-08-ST ASM5I23S04AG-2-08-SR ASM5I23S04AG-2-08-ST ASM5P23S04AG-2H-08-SR ASM5P23S04AG-2H-08-ST ASM5I23S04AG-2H-08-SR ASM5I23S04AG-2H-08-ST 5P23S04AG-2 5P23S04AG-2 5I23S04AG-2 5I23S04AG-2 5P23S04AG-2H 5P23S04AG-2H 5I23S04AG-2H 5I23S04AG-2H 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green 8-pin 150-mil SOIC-TAPE & REEL, Green 8-pin 150-mil SOIC-TUBE, Green Device Ordering Information ASM5P23S04A F-08-SR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 14 of 15 September 2005 rev 1.3 ASM5P23S04A Alliance Semiconductor Corporation 2575 Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM5P23S04A Document Version: 1.3 Note: This product utilizes US# 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3 Zero `SpreadTrak' Delay Buffer Notice: The information in this document is subject to change without notice. 15 of 15 |
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